IEEE International Symposium on Multiple-Valued Logic (ISMVL)

Outstanding Contributed Paper Award

Date of the award presentation: May 19, 2006 (ISMVL-2006, Singapore)

Award winners (Authors of the paper): Katsuhiko DEGAWA (Tohoku Univ.), Takafumi AOKI (Tohoku Univ.), Tatsuo HIGUCHI (Tohoku Inst. of Technol.), Hiroshi INOKAWA (Shizuoka Univ.), and Yasuo TAKAHASHI (Hokkaido Univ.)

Title of the paper: A Two-Bit-per-Cell Content-Addressable Memory using Single- Electron Transistors

Publication: Proceedings of the 35th IEEE International Symposium on Multiple- Valued Logic (ISMVL), pp. 32-38, Calgary, Canada, May 19-21, 2005.

Summary: This paper presents a circuit design of a two-bit-per-cell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.